An automatically reconfigurable high performance FPGA system that includes a hybrid FPGA network and an automated scheduling, partitioning and mapping software tool adapted to configure the hybrid FPGA network in order to implement a functional task. The hybrid FPGA network includes a plurality of field programmable gate arrays, at least one processor, and at least one memory. The automated software tool adapted to carry out the steps of scheduling portions of a functional task in a time sequence, partitioning a plurality of elements of the hybrid FPGA network by allocating or assigning network resources to the scheduled portions of the functional task, mapping the partitioned elements into a physical hardware design for implementing the functional task on the plurality of elements of the hybrid FPGA network, and iteratively repeating the scheduling, partitioning and mapping steps to reach an optimal physical hardware design.