Methods and apparatus are provided for operating an embedded processor system that includes a processor and a cache memory. The method includes filling one or more lines in the cache memory with data associated with a first task, executing the first task, and, in response to a cache miss during execution of the first task, performing a cache line fill operation and, during the cache line fill operation, executing a second task. The cache memory may notify the processor of the line fill operation by generating a processor interrupt or by notifying a task scheduler running on the processor.