A semiconductor device wherein an avalanche withstand of power MISFET is improved without enlarging cell pitch. In the semiconductor device, impurity ions having a p-type conduction, e.g. B ions, are introduced from a bottom of a contact hole to form a p-type semiconductive region that is provided below a p⁺-type semiconductive region and in contact with the p⁺-type semiconductive region and an n^--type single crystal silicon layer and that has an impurity concentration lower than the p⁺-type semiconductive region. An n-type semiconductive region is formed in the n^--type single crystal silicon layer provided below the p-type semiconductive region as being in contact with the p-type semiconductive region and has an impurity concentration lower than the n^--type single crystal silicon layer.