An address output apparatus capable of retaining a pre-extension upper compatibility of software post memory extension and of accessing separated RAM areas by consecutive addresses, without needing to alter CPU architecture. The address output apparatus includes an address conversion circuit 20 that allots to a RAM 30 a basic RAM area and a first area, being one of two area obtained by dividing an extension RAM area, allots to a RAM 50 a second area, being an area other than the first area of the extension RAM area, and converts logical address signals designated by a CPU 10 to physical address signals based on a state of the allotting.