The concurrent memory control turbo decoder solution of this invention uses a
single port main memory and a simplified scratch memory. This approach uses an
interleaved forward-reverse addressing which greatly relieves the amount of memory
required. This approach is in marked contrast to conventional turbo decoders which
employ either a dual port main memory or a single port main memory in conjunction
with a complex ping-ponged scratch memory. In the system of this invention, during
each cycle accomplishes one read and one write operation in the scratch memories.
If a particular location in memory, has been read, then that location is free.
The next write cycle can use that location to store its data. Similarly a simplified
beta RAM is implemented using a unique addressing scheme which also obviates the
need for a complex ping-ponged beta RAM.