A structure and method of manufacture for an improved multi-chip semiconductor
package that reduces package resistance to a negligible level, and offers superior
thermal performance. Housing of multiple dies is facilitated by providing electrically
isolated lead frames that are separated from a common base carrier by a non-conductive
layer of laminating material. A silicon die is attached inside a cavity formed
in each lead frame. Direct connection of the active surface of the silicon die
to the printed circuit board is then made by an array of solder bumps that is distributed
across the surface of each die as well as the edges of the lead frame adjacent
to each die.