A technique for mapping a plurality of configurable logic blocks in a programmable logic device, such as a field-programmable gate array (FPGA). The method includes adaptively adjusting one or more customer-specified constraints and can be implemented, for example, using a simulated annealing algorithm. During the refinement of the placement (i.e., assignment) of logic blocks in an FPGA, one or more constraints are adjusted by either selecting a customer-specified constraint value or specifying a new constraint value derived based on the actual circuit performance. The method provides substantial savings of computer time compared to the prior art placement methods and improves circuit performance, e.g., by enabling higher circuit operation frequencies.