A digital technique for pulse width modulation (PWM) utilizes a tapped delay line 304 receiving a reference clock and generating a plurality of time delayed reference clock transitions having finer time resolution than the reference clock signal. A multiplexer 120 receives the plurality of time delayed reference clock transitions as an input thereto and producing an output when one of the plurality of time delayed reference clock transitions is addressed. An accumulator circuit 524 generates control timing signals associated with the input signal sampling rate F_sample that are used to select outputs from the delay line 304 representing a pulse width modulated output signal.