In a system having a plurality of processors 1 to M and each processor has corresponding output registers 1 to N an apparatus and method to transfer is claimed. The data comprises a current group of data and a next group of data. Each group of data comprises a plurality of portions of data. The current group of data from each processor 1 to M is transferred to its corresponding output register 1 to N. Each processor then receives and processes the next group of data. Simultaneously, the portion of data from output register N to output register N-1 is transferred. Similarly, each portion of data from output register N-1 is transferred to output register N-2, and so on. The portion of data from register 1 is transferred to a frame buffer.