Provided is directed to an internal supply voltage generator for a delay locked loop circuit which can prevent a tAC for a next read command from being outputted with a delay, by blocking a supply voltage VDLL from a transient lowering regardless of a reacting speed of a VDLL supply voltage generator by means of maximizing a driving power of the VDLL supply voltage generator which generates the supply voltage VDLL of a delay locked loop during entering time from a power down period to a power up period. Furthermore, as the supply voltage VDLL is prevented from lowering without rising the reacting speed of the VDLL supply voltage generator, it is advantageous to prevent a distorting phenomenon of the supply voltage VDLL in response to a fast reacting speed of the VDLL supply voltage generator.