A data line drive circuit is equipped with a single line driver 300 and a gate voltage generation circuit 400. The single line driver 300 is constructed such that N groups (where N is an integer 2 or larger) of series connections of drive transistors 21 to 28 and switching transistors 81 to 88 are connected in parallel. The gate voltage generation circuit 400 includes two transistors 71 and 72 constituting a current mirror circuit, a drive transistor 73, and a constant voltage generation transistor 31. The range of an output current I_out can be controlled by changing any of the design values of the parameters including: relative values K_a and K_b of the gain coefficient for the transistors 31 and 32, the source voltage VDREF of the gate voltage generation circuit 400, and the gate signal VRIN of the drive transistor 73.