An addressing circuit includes a first set of inputs configured to receive a first set of address signals en route from the set of processors to the memory and defining a least significant address portion. The addressing circuit further includes a second set of inputs configured to intercept a second set of address signals en route from the set of processors to the memory and defining a most significant address portion. The addressing circuit also includes control circuitry configured to output a replacement set of address signals to the memory in place of the second set of address signals. The replacement set of address signals defines either the most significant address portion defined by the second set of address signals when the least significant address portion is outside a predetermined range, or a predefined most significant address portion when the least significant address portion is within the predetermined range.

 
Web www.patentalert.com

< Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange

< Methods and structure for preserving lock signals on multiple buses coupled to a multiported device

> Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages

> Storage subsystem having plural storage systems and storage selector for selecting one of the storage systems to process an access request

~ 00245