A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed. The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires or the width of the ground wires. The disclosed method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedances at the junction between the branches are substantially equal.

 
Web www.patentalert.com

< Contrast based resolution enhancing technology

< Method and apparatus for specifying a distance between an external state and a set of states in space

> Delay diagnosis method for semiconductor integrated circuit, computer program product for diagnosing delay of semiconductor integrated circuit and computer readable recording medium recording program thereon

> Post processor for optimizing manhattan integrated circuits placements into non manhattan placements

~ 00246