A stacked multi-chip package is described in which a base die is electrically connected to both an interconnect structure (e.g., a lead frame or a substrate) and a stacked die. A first encapsulant is used to cover some, but not all of the bond pads on a base die as well as portions of their associated electrical connectors (e.g. bonding wires). A surface of the first encapsulant is arranged to support the stacked die. The stacked die is directly electrically connected to bond pads that are not covered by the first encapsulant. A second encapsulant at least partially encapsulates the base and stacked dice and the various electrical connectors. With this arrangement, a stacked multi-chip semiconductor package is provided that includes a direct die-to-die electrical connection. The described arrangement is particularly well suited for use in packages, such as many power packages, in which at least one of the bond pads on the die is centrally located on the active surface of the die and the first encapsulant covers at least a portion of an electrical connector attached to the centrally located bond pad.