The present invention is generally directed to an apparatus and method for accessing
registers within a processor. In accordance with one embodiment, an apparatus and
method are provided for a processor in which at least two separate indicia (such
as register select lines, register bank identifiers, processor mode identifiers,
etc.) are utilized to uniquely identify and access a processor register. In accordance
with this embodiment, bit lines of the separate indicia are encoded into a single,
mapped set of signal lines, and these encoded signal lines are used to access the register.