An integrated system comprises an authorization device that generates a second encrypted data stream in response to a first data stream, and a programmable logic device (PLD) that generates a third encrypted data stream in response to the first data stream, while simultaneously operating under at least partial control of program code during a first time interval This third encrypted data stream is preferably generated internal to the programmable logic device. Authorization detection circuitry is also preferably provided that compares the second and third encrypted data streams at least periodically during the first time interval. This circuitry may also disable operation of the programmable logic device if the second and third encrypted data streams indicate that the programmable gate array is not authorized to use the program code. The authorization detection circuitry is preferably provided within the programmable logic device and may utilize at least a portion of the proprietary program code (e.g., "deadman" code) to perform its operations. Disabling operation of the programmable logic device may constitute a complete shut down of the programmable logic device or the performance of the programmable logic device may be degraded sufficiently to render it unacceptable in the desired application.