A bus macro for use as a routing resource for partial reconfiguration of a field
programmable gate array (FPGA) with a design that has interdesign routing with
at least one other design programmed into the FPGA comprises: at least one row
of bus lines disposed within the FPGA between at least two design areas; a first
set of gates disposed within the FPGA for controlling a routing of signals over
the at least one row of bus lines from a first design area to a second design area
of the FPGA according to a first routing configuration embedded in the first design
area; and a second set of gates disposed within the FPGA for controlling a routing
of signals over the at least one row of bus lines from the second design area to
the first design area of the FPGA according to a second routing configuration embedded
in the second design area. A method of partially reconfiguring a field programmable
gate array (FPGA) with at least one design that has interdesign routing with at
least one other design programmed into the FPGA is also disclosed utilizing at
least one bus macro.