A semiconductor storage apparatus according to one embodiment of the present invention, comprising: a cell array including a plurality of memory cells, each being connected to bit lines and word lines arranged in a row direction and a column direction; and a sense amplifier which controls read-out of data stored in the memory cells, wherein the sense amplifier includes: a pair of sense nodes provided corresponding to a pair of the bit lines; a connection switching circuit connected between the pair of bit lines and the pair of sense nodes, which connects electrically the pair of bit lines and the pair of sense nodes when a write control signal is in a prescribed logic level; and a timing control circuit which sets the write control signal to the prescribed logic level substantially at the same time as a timing when a column selection signal selects a column to which the memory cell to be written is connected during data writing period for the memory cells, and holds the write control signal to the prescribed logic level during a first period regulated by the timing when the column selection signal selects the columns.