A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.

 
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< Processing device with prefetch instructions having indicator bits specifying cache levels for prefetching

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> System, method and apparatus for conserving power consumed by a system having a processor integrated circuit

> System and method for electrical power management in a data processing system using registers to reflect current operating conditions

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