A technique improves the performance of an integrated circuit design by selectively
replacing low Vt transistors with standard Vt transistors.
The selection of gates for replacement may be based on a multi-path timing analysis.
If a low Vt variant of a gate instance increases a path cycle time as
compared to a standard Vt counterpart, the maximum of the path cycle
times for all paths that include the low Vt variant and the maximum
of the path cycle time for these paths with a standard Vt variant are
calculated. If the maximum path cycle time for the path including the low Vt
variant is greater than the maximum path cycle time for the path including
the standard Vt variant, then that low Vt variant is substituted
with a standard Vt variant. Thus, integrated circuit designs prepared
in accordance with the invention may exhibit improved cycle times.
