A transport convergence (TC) subsystem for use as a form of logical pipeline processor is disclosed. The TC subsystem includes a number of ASIC computing blocks interconnected through a local bus for transferring data objects used as a form of common data I/O for each ASIC. The data object includes both control and data portions. A TC scheduling circuit coordinates transfer of data objecst to and from a TC data object memory that is local or external. The TC data object memory is shared in common with all the ASIC blocks so that computation results from each ASIC TC signal processing circuit can be passed between other ASICs to form a logical pipeline. The data objects output from the TC subsystem are used by other processing subsystems in an xDSL communications system, including a software based ATM TC subsystem, and a physical medium dependent subsystem. In addition, the architecture of the TC subsystem is configured so that it can be shared by multiple ports in an xDSL system. The individual ASICs are also adapted to be multi-tasking to further reduce hardware requirements.