A memory driving circuit has a register for receiving a new-coming data and a delayed clock, and exporting a current-existing data. The delayed clock has a delay to a clock. A pre-detecting circuit receives the current-existing data, the new-coming data, and a pre-enable signal, and exports an output signal. Wherein, the current-existing data is compared with the new-coming data. The output signal indicates a disable state if the two data are the same. Otherwise, the output signal indicates an enable state, wherein the pre-enable signal is also used to enable or disable the pre-detecting circuit. An output driving circuit receives the current-existing data and an enabling signal, and exports a first output signal. A pre-driving circuit receives the output signal of the pre-detecting circuit and an enable control signal, and exports a second output signal. An I/O pad receives the first output signal and the second output signal.