The present invention relates to a method for designing a hierarchical, multi-layer integrated circuit (IC) chip design in which a first stage design at a lower level of the hierarchical design provides details of circuit features that occupy areas of the design, and in a higher level stage of the design process corresponding to a higher level of the hierarchy, those details are used to determine free areas in the lower level design that are not yet occupied by circuit features, and allowing further processing of those free areas during the higher level design stage. For example, this may include identifying free tracks within a basic power grid layer and implementing additional power wiring within that power grid layer without having to redo the lower level design.