A DF signal averaging circuit includes a counter for counting a clock signal fed from a clock signal generator, an OR circuit which causes the counter to perform count-up operation only when a transistor is in an ON state with the clock signal and a potential signal fed from the clock signal generator and a positive electrode of the transistor, respectively, a memory circuit for calculating an averaged DF signal from output values of the counter with specific timing, and a preset control circuit for calculating a preset value for the counter from the averaged DF signal fed from the memory circuit and setting the preset value in the counter with specific timing. The averaged DF signal output from the memory circuit is transmitted to an external control unit which is an ECU of a vehicle via a communication interface.