In a clock generating circuit, clocks generated therein are distributed by a clock distribution control circuit for every circuit block. In a clock output control circuit, a clock command is decoded by a clock command decoder and output of the clocks is controlled for every circuit block. A data transfer control device having a clock control circuit functions as a first device or a second device to transfer data as a host or a peripheral. When the data transfer control device function as a second device and in an idle state, it controls clock output to a state controller which controls switching between a host function and a peripheral function.