A system and method for a programmable threshold detector. A programmable threshold detector circuit is described comprising an offset current generator circuit, a comparator circuit, a programmable delay circuit, and a counter timer coupled together. The offset current generator circuit generates a programmable offset current that is associated with a programmable offset voltage. The comparator circuit compares an input signal to a programmable offset voltage. The programmable delay circuit provides a capacitance controlled time delay before asserting a standby mode for the device when the input signal is less than the programmable offset voltage. The counter timer provides a counter controlled time delay before deasserting the standby mode when the input signal is greater than the programmable offset voltage.