A data processing apparatus 2 supports multiple memory access program instructions LDM, STM which serve to load data values from multiple program registers 16 to respective memory locations or to store data values from multiple memory locations to respective program registers. A memory management unit 8 within the system stores device or strongly ordered memory attribute values which control whether or not a multiple memory access instruction involving such a memory location may be early terminated when an interrupt is received during its operation. Early termination is permitted in those circumstances where the multiple memory access instruction may be safely restarted and rerun in its entirety, whereas early termination is not permitted and the operation completes before the interrupt is taken in those circumstances where the memory locations are subject to a guaranteed number of memory accesses as this appears within the controlling program instructions.