A system extends the execution time of a pipeline stage to a time longer than the time interval between two consecutive input data. Each processor in the system has an input and output port connected to a "bypass switch" (or multiplexer). Input data is sent either to a processor, for processing, or to a processor output port, in which case no processing is performed, through a register using at least one clock cycle to move data from register input to register output. For a single channel requiring an execution time twice the time interval between two consecutive input data, two processors are interconnected by the bypass switch. Data flows from the first processor at the input of the system, through the "bypass switches" of the interconnected processors, to output. The "bypass switches" are configured with respect to the processors such that the system data rate is independent of processor number.