The present invention relates to a cache (10) and system and method of
maintaining cache coherency in a parallel processing system, by tagging (13)
cached data (11) with the identity of the users or process threads which
have access rights to the data. Cache users may see a cache miss even if the data
is in the cache, unless they have access rights. The tags can be reset to disallow
further access on thread transfer or at the point of synchronisation of process threads.