A clock distribution architecture having clock and power failure protection is disclosed. In one embodiment, a computer system includes a plurality of client boards and a plurality of switch boards, as well as having power distribution boards and clock boards (referred to herein as service processor boards). In one embodiment may include a clock board and a plurality of power distribution boards, while another embodiment may include a power distribution board and a plurality of clock boards. The clock board(s) may generate a global clock signal, which may be distributed to the switch boards and the power distribution board(s). The power distribution board(s) may distribute the global clock signal to the client boards. Clock redundancy may be provide through either having multiple clock boards or multiple power distribution boards.