A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.

 
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< Polarizable electrode for electric double-layer capacitor, process for producing the polarizable electrode and process for producing the electric double-layer capacitor

< Semiconductor memory devices with delayed auto-precharge function and associated methods of auto-precharging semiconductor memory devices

> Semiconductor memory device for reducing current consumption in operation

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