A delay-locked loop (DLL) capable of directly receiving external clock
signals is provided. The DLL comprises a level selector, a control signal
generator, and an internal clock signal generator. The level selector
receives an external clock signal, and directly outputs the external
clock signal, or changes a level of the external clock signal and outputs
a changed external clock signal, in response to a control signal. The
control signal generator generates the control signal. The internal clock
signal generator receives an output signal of the level selector and the
external clock signal, and generates an internal clock signal
synchronized to a phase of an output signal of the level selector.