A processing system comprising: i) a read-only memory (ROM) that stores original ROM code; ii) a custom array that stores replacement ROM code; and iii) control logic that receives an incoming ROM address and a read request signal generated by a source device. The control logic, in response to receipt of the incoming ROM address and the read request signal, compares the incoming ROM address to a patched address associated with the ROM. If a match occurs, the control logic outputs to the custom array a translated address associated with the patched address. The custom array then outputs a first line of replacement ROM code associated with the translated address.