A distributed processing system having a host processor including a host communication infrastructure (HCI) configured for communication with said host processor; a plurality of class processors each having an associated private localized read/write memory; and a plurality of application program interface modules each configured to provide an interface between said host communication infrastructure and at least one said class processor, wherein each said class processor responds to selected data messages on said HCI to perform selected computations utilizing said read/write memory. This embodiment provides an ideal architecture for fabrication on a single chip and avoids processor and bus bottlenecks by providing distributed processing power with local memory for each class processor.Also provided is a method for designing a distributed processing system for an application. The method includes steps of partitioning the application into functions and data messages; configuring a host processor having a host communication infrastructure (HCI) to pass data messages via the HCI to control the application; configuring a plurality of class processors to compute the functions into which the application is partitioned in response to the data messages; and interconnecting the class processors to the host processor via application program interface modules in a star configuration. Systems designed in accordance with this method embodiment are well-suited for integration on a single chip, and can be easily updated and modified as necessary, because changes made to a class processor have minimal effect on the remainder of the system.