A design of a vertical cavity surface emitting laser chip suitable for high speed data communication. An intracavity contact to the doped layers of the bottom mirror is formed so that both contacts are on the top epitaxial side of the wafer. These main structural features can be used to reduce the bond pad capacitance by a suitable spatial separation of metallizations of the p and n contact. The bond pads are processed as a short symmetric coplanar line in a ground signal ground configuration which allows flexible device testing and packaging. A significant capacitance between the pads of the center strip and the outer ground strips is avoided by etching the doped semiconductor layers between these strips down to the semi-insulating substrate. This design avoids pad metallizations and the corresponding critical photolithographic steps over large height differences from the vertical cavity surface emitting laser mesa top to the substrate. This insures good lithographic fidelity and makes the process reproducible.