An apparatus including a plurality of first base circuits, a plurality of
second base circuits, a first test circuit, a second test circuit, and a
test path. The plurality of first base circuits may be coupled to the
plurality of second base circuits via one or more base circuit paths on a
layout. The first test circuit may be disposed in a first distal location
of the layout. The second test circuit may be disposed in a second distal
location of the layout. The test path may be configured to (i) couple the
first test circuit to the second test circuit and (ii) generate a test
time delay from the first test circuit to the second test circuit
incrementally longer than a maximum time delay generated by any of the
base circuit paths.