A semiconductor memory device includes a memory cell including a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; a switching transistor circuit including a negative voltage switching circuit for applying a negative voltage to the gate electrode of the memory cell, and a switching transistor connected to an output of the negative voltage switching circuit and a first voltage source for outputting a voltage having a voltage level lower than zero volt; a pull-up circuit connected to a control terminal of the switching transistor and selectively connected to a second voltage source for outputting a voltage having a voltage level higher than zero volt; and a pull-down circuit connected to the first voltage source and the control terminal of the switching transistor.