A memory device that amplifiers read data based on the timing of a CLK signal input from an external device comprises: a delay circuit 5 that controls a code of the CLK signal and a delay amount based on a CT signal input from an external device to output a CLK_delay signal; a sense enable signal generation section 6 that generates a sense enable signal based on the CLK_delay signal; a memory cell 4 that outputs data in accordance with an instruction from outside; and a sense amplifier 7 that amplifiers the output of the memory cell in accordance with the sense enable signal.