A bus layout design is provided which includes a first electrically conductive layer with a first bus and a second bus and a second electrically conductive layer with a first bus and a second bus. Vias are provided between the first electrically conductive layer and the second electrically conductive layer such that the first bus and the second bus of the first electrically conductive layer are electrically connected.

 
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< Semiconductor element

< Stacked switchable element and diode combination

> Large-area nonenabled macroelectronic substrates and uses therefor

> Semiconductor integrated circuit device and its manufacturing method

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