The disclosed nonvolatile ferroelectric memory device comprises: a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of platelines, respectively; a read control block configured to convert the data level voltage stored in the memory cell into a corresponding data bit value of a plurality of data bit values and output the converted value externally; and a write control block configured to write a plurality of bit data inputted externally as a corresponding data level voltage of a plurality of data level voltages in the memory cell, wherein bitlines are layered into main bitline and sub-bitline by reducing a current value corresponding to a sensing voltage of the sub-bitline at an initial level of the main bit line. As a result, the FRAM can write a plurality of data levels in one ferroelectric memory cell.