A phase adjuster (10) includes a delay-locked loop (14) and an interpolator (34). The delay-locked loop (14) includes a sufficient number of delay stages (24) to maintain a .PI./2 radians phase shift across the one delay stage (24') of a voltage-controlled delay line (20). The output signals (28 and 30) to this one stage (24') are filtered, output from the delay-locked loop (14), and input to the interpolator (34). Within the interpolator (34), these output signals (28 and 30) are weighted and combined. The ratio of the weighting applied to the output signals determines the resulting adjusted phase of an output clock signal (36). The weighting can be a time-varying signal or otherwise programmed as needed to achieve a desired phase shift that is independent of clock speed and process variation.