One or more secondary data structures are maintained containing mappings of logical flash memory addresses to physical flash memory addresses. Each secondary data structure has a predetermined capacity of mappings. A master data structure is also maintained containing a pointer to each of the one or more secondary data structures. Additional secondary data structures are allocated as needed to provide capacity for additional mappings. One or more counters associated with each of the one or more secondary data structures, respectively, provides an indication of when each of the one or more secondary data structures reaches the predetermined capacity of mappings.