In general, in one aspect, the disclosure describes an apparatus that includes a plurality of flow controllable queues containing data to be transmitted. The queues are organized by flow. The apparatus also includes a plurality of destinations to receive data from the plurality of queues. The apparatus further includes a controller to continually maintain an aggregate count of data ready for transmission to the destinations and determine next queue to transmit data from based at least partially on the aggregate counts.

 
Web www.patentalert.com

< Integrated memory mapped controller circuit for fiber optics transceiver

< Arrangement for automated fault detection and fault resolution of a network device

> VLIW computer processing architecture having the problem counter stored in a register file register

> Testing a programmable logic device with embedded fixed logic using a scan chain

~ 00276