A programmable interconnect structure in an integrated circuit comprising: a plurality of wires; and a buffer comprising an input and an output, said buffer receiving a weak signal at the input and providing a buffered signal at the output; and a first programmable multiplexer comprising: a plurality of inputs and an output, wherein the inputs are coupled to said plurality of wires, and the output is coupled to said input of the buffer; and a user configurable configuration circuit comprising a plurality of memory elements, wherein the data stored in the memory elements select one of said plurality of wires to couple to said buffer input; and a second programmable multiplexer comprising: an input and a plurality of outputs, wherein the input is coupled to said output of the buffer and the outputs are coupled to said plurality of wires; and a user configurable configuration circuit comprising a plurality of memory elements, wherein the data stored in the memory elements select said buffer output to couple to one of said plurality of wires; wherein, a signal received by the buffer on any one of the plurality of wires is buffered and transmitted to one or more of the other wires. The area of the structure is significantly reduced by increasing the number of programmable switches, generating a layout efficient wire sharing multiplexing scheme, moving the memory elements to a vertical position and using a single large area output stage in the buffer.