Methods of operating a memory device comprised of a plurality of arrays of memory cells and peripheral devices for reading and writing information to the memory cells. One method comprises outputting an n-bit word in two 1/2n bit prefetch steps from a plurality of memory arrays in response to an address bit. Another method comprises prefetching a first portion of a word from a memory array, and prefetching a second portion of the word from the memory array, the first and second portions being determined by an address bit. Another method comprises reading a word from a memory array in at least two prefetch operations, wherein the order of the prefetch operations is controlled by an address bit.