A cache memory that notifies other functional blocks in the microprocessor that a miss has occurred potentially N clocks sooner than the conventional method, where N is the number of stages in the cache pipeline. The multiple pass cache receives a plurality of busy indicators from resources needed to complete various transaction types. The cache distinguishes between a first set of resources needed to complete a transaction when its cache line address hits in the cache and a second set of resources needed to complete the transaction type when the address misses in the cache. If none of the second set of resources for the type of the transaction type is busy on a miss, then the cache immediately signals a miss rather than retrying the transaction by sending it back through the cache pipeline and causing N additional clock cycles to occur before signaling the miss.