A microprocessor apparatus for exclusive prefetch and initialization of cache lines, including translation logic and execution logic. The translation logic translates a block allocate and initialize instruction into a micro instruction sequence that directs a microprocessor to prefetch and initialize a block of cache lines. The block allocate and initialize instruction is encoded to direct the microprocessor to prefetch and initialize the block of cache lines. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the block of cache lines in the exclusive state. Upon receipt, the execution logic initializes the block of cache lines to the specified value. The allocation and initialization of the specified number of cache lines occurs in parallel with execution of other instructions in a program flow of an application program.