The multi-port memory device includes a plurality of ports supporting serial I/O interface, and the plurality of ports includes a transmission pad and a reception pad. The multi-port memory device includes: a memory core; a control block for generating an internal command signal, an internal address and a control signal, which correspond to the command and are necessary for an operation of the memory core, using commands and addresses inputted to the plurality of ports packet form; and a mode selection block for combining signals applied to plurality of mode selection pads and generating a test mode flag signal, in which I/O data assigned to the transmission pad and the reception pad in a test mode in response to the test mode flag signal are exchanged with the memory core through the ports.