A data relay controller for decreasing operation load and reducing circuit scale. The controller transfers a data block between a buffer memory and a computer. An access circuit writes the main data to or reads the main data from the buffer memory. An address generation circuit generates address data in accordance with a writing or reading head address of the main data provided from an external device. A counter counts the main data to generate a count value. An address skip control circuit skips the address data by a predetermined number of addresses corresponding to a storage area of the sub data or the parity data in the buffer memory in accordance with the count value and the head address.

 
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< Adaptive prefetch of I/O data blocks

> Re-fetch of long operand buffered remainder after cache line invalidation in out-of-order multiprocessor system without instruction re-execution

> Disk mirror architecture for database appliance

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