A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.

 
Web www.patentalert.com

< Using patterns to perform personal identification data substitution

< Digital camera memory system

> Native lookup instruction for file-access processor searching a three-level lookup cache for variable-length keys

> Method and apparatus for allocating processor resources in a logically partitioned computer system

~ 00282